Various apparatus have been used in the semiconductor packaging industry for detaching a semiconductor chip from an adhesive tape carrier in chip bonding or flip chip bonding processes. This detachment is usually necessary where a slice of wafer comprising a plurality of said semiconductor chips has been mounted onto an adhesive tape (such as Mylar film) for dicing, and each diced chip has to be removed from the adhesive tape and placed at a bonding location. The most commonly-used technique is implemented by using push-up pin(s) or multiple sets of push-up pin(s) together with a vacuum platform, such as disclosed in U.S. Pat. No. 6,386,815 entitled “Pick-up Apparatus for Semiconductor Chips” and U.S. Pat. No. 6,555,418 entitled “Method for Separating a Semiconductor Element in a Semiconductor Element Picking-up Device”.
The first step of the detachment process generally comprises a delamination or peeling action between the semiconductor chip and the adhesive tape, which is induced by an upward force exerted by the push-up pin(s) underneath the chip and adhesive tape, reinforced by suction force from a vacuum platform holding down the adhesive tape. A disadvantage of this technique is that a strong bending moment will be induced on the semiconductor chip if the peeling action is not strong enough to overcome the interfacial adhesion. The chip will experience high compressive stress at the location(s) directly above the push-up pin(s). The chip will be susceptible to crack failure if the strain induced by this bending moment exceeds its critical strain. For very thin semiconductor chips (especially with a thickness of less than 150 microns), that can lead to a major failure of the chip detachment process.
In addition, as the size of the semiconductor chip increases, the ejector pin(s) need to move further upwards in order to allow delamination between the chip and the adhesive tape to propagate inwards into an inner portion of the chip. However, increasing the elevation height of the ejector pin(s) will increase the susceptibility of the chip to chip-crack failure. Another technique relies on the vacuum suction provided by a supporting platform, such as that disclosed in U.S. Pat. No. 6,202,292 (“Apparatus for Removing a Carrier Film from a Semiconductor Die”), U.S. Pat. No. 6,505,395 (“Apparatus and Method for Removing Carrier Tape from a Singulated Die”) and U.S. Pat. No. 6,658,718 (“Method for Removing Carrier Film from a Singulated Die”). A strong vacuum suction via a suitably-structured platform tends to pull the adhesive tape away from the semiconductor chip. The chip will then be supported by the highest points of the structure and be ready for pickup. A disadvantage of this technique is that the geometry and form factor of the structure, as well as the strength of the vacuum suction provided, tend to limit the highest interfacial adhesive strength that can be overcome by this design.
Some other techniques introduce objects with various geometries such as a cylinder or bar, such as in U.S. Pat. No. 6,123,800 (“Method and Apparatus for Handling Element on an Adhesive Film”), U.S. Pat. No. 6,165,310 (“Apparatus and Method for Removing Parts from an Adhesive Film”) and U.S. Pat. No. 6,290,805 (“System and Method for Using a Pick and Place Apparatus”). In other examples, a curved surface bar is used in U.S. Pat. No. 6,629,553 (“Method and System for Mounting semiconductor Device, Semiconductor Device Separating System, and Method for Fabricating IC Card”) and a stepped flat plate underneath the semiconductor wafer or the chip(s) is used in U.S. Pat. No. 6,561,743 (“Pellet Picking Method and Pellet Picking Apparatus”). The lateral motion of these objects or tools (as opposed to the vertical motion of tools in traditional methods) on a vacuum platform will create a peeling action to detach the chip(s) from the adhesive tape. In some designs, instead of moving the objects, the objects are stationary but the wafer comprising semiconductor chips are moved laterally across these objects.
Generally speaking, customized tooling is needed for most of these techniques such that careful optimization of their geometries is necessary to ensure successful detachment and to avoid crack failure. The risk of crack failure will become pronounced if the thickness of the chip is reduced to below 150 microns (6 mils). Three major factors affecting the ability of the detachment process to successfully delaminate a chip are: (i) thickness of the semiconductor chip, (ii) the size of the semiconductor chip, and (iii) the adhesion strength of the adhesive tape. Therefore, the process window for successful detachment depends very much on the geometries of the toolings and limits the flexibility, efficiency and reliability of these techniques.
In another prior art method, the adhesion strength between the semiconductor chip and the adhesive tape may be reduced by UV light when a UV dicing tape is used. The adhesion strength of this tape can be reduced by more than two orders after exposure to UV light. After UV exposure the adhesive strength of this tape can be as small as approximately 10-30 gf/20 mm. One of the major concerns for all existing semiconductor chip detachment mechanisms is the small process window for a given tooling if a wafer is very thin (such as having a thickness of less than 150 microns) and/or large (such as having a width larger than 8 mm) and/or the wafer is mounted onto a adhesive tape of high adhesive strength (approximately 50 gf/20 mm). With this small process window, the process throughput and yield may not be easy to optimize, particularly in some cases where the adhesive strength of the tape is not uniform across the whole wafer. For example, it has been found that the peripheral chips around the wafer on a UV tape usually experience higher adhesivity to the UV tape than chips at the center of the wafer. Difficulty may thus be encountered when using the aforesaid prior art techniques in optimizing the process parameters to maximize throughput and yield.